Journal of Electrical & Electronic Systems

Daniel Kho CK

Publications

• Review Article
  Hardware Implementation of Low-Latency 32-bit Floating-Point Reciprocal
  Author(s): Daniel Kho CK, Ahmad Fauzi MF and Lim SLDaniel Kho CK, Ahmad Fauzi MF and Lim SL
  
  As the speed requirements of imaging and communications systems increase, the latency requirements of digital circuits also become stringent. Due to such tight latency or timing requirements, large-stage pipelined circuits need to be redesigned to meet the low-latency requirements. Most modern imaging and communications systems rely on digital signal processing (DSP) that compute complex mathematical operations. The emergence of powerful and low-cost field programmable gate array (FPGA) devices with hundreds of arithmetic multipliers has enabled many such DSP hardware applications, traditionally implemented only as software solutions. The reciprocal square root algorithm is a popular technique for computing square roots, used widely in many software applications. This paper shows how this algorithm can be implemented efficiently on hard ware, and is suitable for lowlatency mathematica.. Read More»
  DOI: 10.4172/2332-0796.1000278

  Abstract PDF