Phase-error correction by single-phase phase-locked loops based on transfer delay

Journal of Electrical & Electronic Systems

ISSN: 2332-0796

Open Access

Phase-error correction by single-phase phase-locked loops based on transfer delay

Global Summit on Electronics and Electrical Engineering

November 03-05, 2015 Valencia, Spain

Patrick Kobou Ngani

University of Luxembourg, Luxembourg

Scientific Tracks Abstracts: J Electr Electron Syst

Abstract :

Comparative studies of different single-phase phase-locked loops (PLL) algorithms have been made. They show that the PLL based on sample delay (dPLL), presents the lowest computational load and is as robust as the three-phase synchronous reference frame PLL dqPLL by input signal amplitude and phase variations. Its weakness appears when the input signal frequency differs from its rated frequency: It depicts a steady error on the calculated signal phase-angle. After a brief review of the dqPLL which constitutes debase structure of the dPLL, the following work will present three methods that improve the phase detection accuracy of dPLL. It is shown that the modifications brought in the original structure do not influence the robustness and stability of the algorithm but reduce the phase angle offset error by input signal frequency variation. This is corroborated by tests including not only the fundamental input voltage disturbance like amplitude, phase and frequency variation but also harmonic voltage distortion.

Biography :

Patrick Kobou Ngani has completed his Master’s degree in Energy and Environment in 2013 at the University of Luxembourg (UL) where he also studied Mechatronics in his Bachelor’s degree. He started his PhD project in 2014 where he is focusing on improving the power quality in low-voltage power grid by mitigating the harmonic distortion voltages using an active filter.

Email: [email protected]

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